spt9101 125 msps sample-and-hold amplifier features ? second source of ad9101 ? 350 mhz sampling bandwidth ? 125 mhz sampling rate ? excellent hold mode distortion -75 db at 50 msps (23 mhz v in ) -62 db at 100 msps (48 mhz v in ) ? 7 ns acquisition time to 0.1% ? <1 ps aperture jitter ? 66 db feedthrough rejection at 50 mhz ? low spectral noise density applications ? test instrumentation equipment ? rf demodulation systems ? high performance ccd capture ? digital sampling oscilloscopes ? commercial and military radar ? high-speed dac deglitching 4x amp - + c h old sampler + - 3r r rtn clk nclk v in v o ut block diagram general description the spt9101 is a high-speed track-and-hold amplifier de- signed for a wide range of use. the spt9101 is capable of sampling at speeds up to 125 msps with resolutions ranging from 8 to 12 bits. trim programmable internal hold and compensation capacitors provide for optimized input band- width and slew rate versus noise performance. the performance of this device makes it an excellent front end driver for a wide range of adcs on the market today. significant improvements in dynamic performance can be achieved by using this device ahead of virtually all adcs that do not have an internal track-and-hold. the spt9101 is offered in 20-lead soic and lcc packages over the industrial temperature range and in die form. contact the factory for military and /833 package options. signal processing technologies, inc. 4755 forge road, colorado springs, colorado 80907, usa phone: (719) 528-2300 fax: (719) 528-2370 website: http://www.spt.com e-mail: sales@spt.com
spt 2 12/30/99 spt9101 dc performance gain d v in = 0.5 v +25 c i 3.93 4.0 4.07 v/v full temp. vi 3.9 4.1 v/v offset d v in = 0 v +25 ci 3 10 mv full temp. vi 30 mv output resistance +25 c v 0.5 w output short circuit current full temp. v 60 ma psrr d v s = 0.5 v p-p +25 cvi3743db pedestal sensitivity to pos. supply full temp. v 4 mv/v d v s = 0.5 v p-p pedestal sensitivity to neg. supply full temp. v 8 mv/v d v s = 0.5 v p-p analog input/output maximum output voltage range 6 full temp. vi 2.4 2.7 v input bias current +25 ci 15 30 m a full temp. vi 35 m a input capacitance +25 cv 2pf input resistance full temp. vi 100 450 k w clock inputs input bias current +25 cvi 330 m a input low voltage full temp. vi -1.8 -1.5 v input high voltage full temp. vi -1.0 -0.8 v track mode dynamics bandwidth (-3 db) v out = 1.0 v p-p full temp. iv 150 180 mhz slew rate 4 v output step full temp. iv 1100 1400 v/ m s overdrive recovery time 1 to 0.1% v 55 ns integrated output noise bw = 5 to 200 mhz v 270 m v input rms spectral noise 10 mhz v 3.9 nv hz absolute maximum rating (beyond which damage may occur) 1 electrical specifications +v s =+5.0 v, -v s =-5.2 v, r load =100 w , unless otherwise specified. test test spt9101 parameters conditions level min typ max units note 1: operation at any absolute maximum ratings is not implied. see electrical specifications for proper nominal applied conditions in typical application. output currents continuous output current ................................... 70 ma temperature operating temperature .............................. -40 to +85 c junction temperature ......................................... +150 c lead, soldering (10 seconds) ............................. +220 c storage ..................................................... -65 to +150 c supply voltages supply voltage (+v s ) ................................ -0.5 v to +6 v supply voltage (-v s ) ................................. -6 v to +0.5 v input voltages analog input voltage ................................................ 5 v clk, nclk input ....................................... -5 v to +0.5 v
spt 3 12/30/99 spt9101 electrical specifications +v s =+5.0 v, -v s =-5.2 v, r load =100 w , unless otherwise specified. test test spt9101 parameters conditions level min typ max units hold mode dynamics worst harmonic 23 mhz, 50 msps v -75 db fs v out = 2 v p-p +25 c worst harmonic 48 mhz, 100 msps iv -62 -57 db fs v out = 2 v p-p +25 c worst harmonic 48 mhz, 100 msps iv -53 db fs v out = 2 v p-p full temp. worst harmonic 48 mhz, 125 msps v -57 db fs v out = 2 v p-p +25 c sampling bandwidth 2 -3 db, +25 ?c v 350 mhz v in = 0.5 v p-p hold noise 3 (rms) +25 c v 150 x t h mv/s droop rate v in =0.0 v, +25 c v -40 mv/ m s feedthrough rejection (50 mhz) full temp. v -66 db v out = 2 v p-p maximum hold time, v in =0 v full temp. iv 100 200 ns track-and-hold switching aperture delay +25 c v -250 ps aperture jitter +25 c v <1 ps rms pedestal offset, v in =0 v +25 ci 10 25 mv full temp. vi 35 mv transient amplitude v in = 0 v, full temp. v 8 mv settling time to 4 mv full temp. v 4 ns glitch product 4 +25 c v 20 pv-s v in = 0 v hold-to-track switching acquisition time to 0.1% +25 cv7ns 2 v output step acquisition time to 0.01% +25 civ1114ns 2 v output step full temp. iv 16 ns power supply 5 +v s voltage full temp, track mode vi 54 65 ma full temp, clocked mode vi 44 55 ma -v s voltage full temp, track mode vi 54 65 ma full temp, clocked mode vi 44 55 ma power dissipation full temp, track mode vi 551 663 mw full temp, clocked mode vi 449 561 mw 1 time to recover within rated error band from 160% overdrive. 2 sampling bandwidth is defined as the -3 db frequency response of the input sampler to the hold capacitor when operating in the sampling mode. it is greater than tracking bandwidth because it does not include the bandwidth of the output amplifier. 3 hold mode noise is proportional to the length of time a signal is held. for example, if the hold time (t h ) is 20 ns, the accumulated noise is typically 3 m v (150 mv/s x 20 ns). this value must be combined with the track mode noise to obtain total noise. 4 total energy of worst case track-to-hold or hold-to-track glitch. typical thermal impedances: q jc (lcc) = +6 c/w q ja (soic) = +85 c/w in still air at +25 c ambient. 5 clocked mode is specified with a 50% clock duty cycle. 6 analog input voltage should be limited 0.8 volts to maintain device in linear range.
spt 4 12/30/99 spt9101 figure 1 - timing diagram timing specification definitions acquisition time this is the time it takes the spt9101 to acquire the analog signal at the internal hold capacitor when it makes a transition from hold mode to track mode. (see figure 1.) the acquisition time is measured from the 50% input clock transition point to the point when the signal is within a specified error band at the internal hold capacitor (ahead of the output amplifier). it does not include the delay and settling time of the output amplifier. because the signal is internally acquired and settled at the hold capacitor before the output voltage has settled, the sampler can be put in hold mode before the output has settled. track-to-hold settling time the time required for the output to settle to within 4 mv of its final value. aperture delay the aperture delay time is the interval between the leading edge transition of the clock input and the instant when the input signal was equal to the held value. it is the difference in time between the digital hold switch delay and the analog signal propagation time. because the analog propagation time is longer than the digital delay in the spt9101, the aperture delay is a negative value. acquisition time aperature delay track-to-hold settling hold track hold clk nclk output input observed at hold capacitor observed at amplifier output test level codes all electrical characteristics are subject to the following conditions: all parameters having min/ max specifications are guaranteed. the test level column indicates the specific device test- ing actually performed during production and quality assurance inspection. any blank sec- tion in the data column indicates that the speci- fication is not tested at the specified condition. test level i ii iii iv v vi test procedure 100% production tested at the specified temperature. 100% production tested at t a =25 c, and sample tested at the specified temperatures. qa sample tested only at the specified temperatures. parameter is guaranteed (but not tested) by design and characterization data. parameter is a typical value for information purposes only. 100% production tested at t a = 25 c. parameter is guaranteed over specified temperature range.
spt 5 12/30/99 spt9101 figure 2 - typical interface circuit -a5.2 clk in v t + 2.2 f + 2.2 f spt, hcmp96850 v ee v cc gnd le in- v out v in spt9101 -v s -v s -v s -v s +v s +v s +v s +v s 6,7,16 1,2 15 18 4589 12 13 17 18 gnd rtn nclk clk 10 11 +a5 -a5.2 in+ 1,16 12 11 -a5.2 220 330 220 330 -a5.2 +a5 8 2 3 4 v in v out 6 x 1) v t = threshold voltage: -a5.2 v t 1k 3k +a5 v t 1k 3k notes: a) for ttl or cmos clock input b) for ecl clock input 2) unless otherwise specified, all capacitors are 0.01 or 0.1 f, surface mount. 3) x = termination (if required). 4) clkin a) ttl/cmos b) ecl: direct input 96850 r clkin r theory of operation the spt9101 is a monolithic 125 msps track and hold amplifier built on a very high-speed complementary bipolar process. it is pin and functionally compatible with the ad9101. it is a two stage design with a sampler driving a hold capacitor followed by a noninverting output buffer amplifier with gain of 4. the first stage sampler is based on a current amplifier in noninverting gain of one configuration with inverting input connected to the output. the hold switch is integrated into this closed-loop first stage amplifier. the output buffer amplifier is in a noninverting gain of 4 configuration with inverting input connected to a resistor divider driven from the output. the noninverting input from the hold capacitor employs input bias current cancellation which results in excellent droop rate performance. the sampler and amplifier stages both employ complementary current ampli- fiers for high-speed, low-distortion performance. typical interface circuit bootstrap capacitor the spt9101 does not require the bootstrap capacitor that is required on the ad9101 between pins 3 and 19. because pins 3 and 19 are no connects on the spt9101, it will work well in existing ad9101 sockets. clock driver circuit (clk, nclk pins) spt highly recommends that a differential ecl clock be used to drive the spt9101. both the 10kh and 100kh family of ecl logic can be used. the typical interface diagram, figure 2, shows the use of a spt hcmp96850 high-speed com- parator. the comparator has a typical propagation delay of 2.4 ns, very low offset of 3 mv, and a minimum tracking bandwidth of 300 mhz. the comparator shown has been set up in a feedthrough operation mode with latch enable con- nected to a logic high. the threshold voltage (v t ) can be set using a resistor divider as shown in note 1 of figure 2. the configuration shown in note 1a is for a ttl/cmos clock input and the configuration shown in note 1b is for an ecl clock input. the differential output of the comparator is directly fed to the spt9101 clock input. the comparator can also be driven with a sinewave input, with the threshold voltage (v t ) adjusted to produce the desired track/hold duty cycle ratio. note 4a shows the resistor divider configuration for a ttl/ cmos clock input. if an ecl clock is used it can be directly fed into the comparator. output level shifting (rtn pin) the rtn pin is tied to the output buffer amplifier internal feedback resistor network as shown in the block diagram. normally this pin is tied to ground for a 4x gain output amplifier configuration. however, this pin may be configured in other ways as long as certain guidelines are met.
spt 6 12/30/99 spt9101 the rtn pin may be tied to an external voltage to generate an offset at the output. v out must be kept to less than 2.7 v typical output swing. v out , with an external reference voltage at the rtn pin, is represented by the following formula: v out = 4 v in - 3 v ref where v ref = voltage at rtn pin and | v out | 2.7 v the following options are generally not recommended due to the possibility of degraded noise performance of the device: the rtn pin can also be tied to an external resistor to reduce the gain but performance may degrade due to increased noise from the external resistor. also rtn can be left open for unity gain mode, however, noise will increase. in all cases, v in must be kept to -0.5 v v in +0.5 v for rated performance. sampler for 12-bit adc application the spt9101 was specifically designed for applications where improved bandwidth performance is required. figure 3 shows as simple block diagram of the spt9101 as a sampler ahead of our spt7922 12-bit, 30 msps adc. figure 3 - sampler for 12-bit adc spt9101 spt7922 v in clock 1 clock 2 12 the graph below entitled improved dynamic performance using the spt9101 shows the performance with and without the spt9101. the spt9101 significantly extends the dy- namic performance range of the converter. performance characteristics spt9101 hold mode distortion vs. temperature -65 -60 -50 -25 0 25 50 75 10 0 temperature (?) db worst harmonic input frequency = 50 mhz clock frequency = 100 mhz hold = 4 ns track = 6 ns spt9101 hold mode distortion vs input frequency -75 -70 -65 -60 -55 1 10 100 input frequency (mhz) db worst harmonic clock frequency = 100 mhz track = 6 ns hold = 4 ns improved dynamic performance using the spt9101 tde (db) 5101520 40 50 60 70 f in (mhz) spt7922 spt9101 & spt7922 (f s = 28 msps) droop rate vs temperature -200 20406080 temperature (?) mv/us -40 0 40 -80 -120
spt 7 12/30/99 spt9101 package outlines 20-lead lcc inches millimeters symbol min max min max a .040 typ 1.02 b .050 typ 1.27 c 0.045 0.055 1.14 1.40 d 0.345 0.360 8.76 9.14 e 0.054 0.066 1.37 1.68 f .020 typ 0.51 g 0.022 0.028 0.56 0.71 h 0.075 1.91 c d f a b pin 1 bottom view g h e 20-lead soic inches millimeters symbol min max min max a 0.291 0.299 7.40 7.60 b 0.394 0.419 10.00 10.65 c 0.496 0.512 12.60 13.00 d 0.050 typ 1.27 typ e 0.014 0.019 0.35 0.49 f 0.004 0.012 0.10 0.30 g 0.093 0.104 2.35 2.65 h 0.009 0.013 0.23 0.32 i 0.016 . 0.050 0.40 1.27 1 20 c g a b de f h i
spt 8 12/30/99 spt9101 rtn rtn n/c v out n/c n/c clk +v s gnd gnd +v s +v s +v s -v s -v s v in gnd nclk -v s -v s 1 20 19 2 3 11 12 13 10 9 16 15 14 17 18 6 7 8 5 4 pin assignments soic pin functions name i/o function rtn i gain set resistor return +v s i +5 v power supply gnd i ground clk i true ecl t/h clock nclk i complement ecl t/h clock -v s i -5.2 v power supply n/c - no connection v in i analog signal input v out o analog signal output ordering information part number package type temperature range spt9101sis 20l soic -40 to +85 c SPT9101SIC 20l lcc -40 to +85 c spt9101scu die* +25 c *please see die specification for guranteed electrical performance. 1 2 3 4 5 6 7 8 9 10 n/c gnd gnd clk rtn rtn +v s +v s +v s +v s 16 15 14 11 12 13 17 18 19 20 -v s -v s v in n/c gnd nclk -v s v out n/c -v s lcc (bottom view) signal processing technologies, inc. reserves the right to change products and specifications without notice. permission is her eby expressly granted to copy this literature for informational purposes only. copying this material for any other use is strictly prohibited . warning - life support applications policy - spt products should not be used within life support systems without the specific written consent of spt. a life support system is a product or system intended to support or sustain life which, if it fails, ca n be reasonably expected to result in significant personal injury or death. signal processing technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device failure. it is therefore not recommended, and exposure of a device to such a process will void the product warranty.
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